Sharjeel Imtiaz Projects
Selected GitHub work from Sharjeel Imtiaz.
GitHub Projects
Hardware security, RISC-V processor design, formal verification, and AI-assisted assertion workflows.
RISC-V Microarchitecture Lab
Designing, verifying, and formally proving a RISC-V microarchitecture with functional and security-oriented verification.
DetailsAutoTrans-RV
AI-assisted automatic translation of RISC-V security assertions using LLMs with formal verification validation.
DetailsAutoAssert-RV
A research pipeline using LLMs to automatically generate formal assertions from RTL hardware designs.
DetailsSingle-Cycle RISC-V RV32I Processor
A Verilog implementation of a single-cycle RV32I RISC-V processor architecture.
Details